Output Channel List Clocking

Technology

System Architecture

DAP Architecture

Processing

Networking

Output Overview

Single-Sample Clocking

Channel List Clocking

Gated

Burst

One-Shot Triggering with Channel-List-Clocking Updates

This configuration can update all analog output channels in rapid sequence based on the internal clock. This pattern of updates is repeated each time the external clock goes active, and the entire process can be initiated by triggering.

animated example of triggering with channel list clocking

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Notes:

Clocking can start when trigger is held active high at least tTrigMin
External clock cycle must be at least tSynch + Nchannels x TIME specification
All clock levels must be held for at least tExtClkPW
Clocking activity begins tTCsetup after triggering goes active
Data from buffer must be fetched and stable at converter before clocking
The first update is latched at the external clock edge
Next sample after interval TIME plus synchronizing delay up to tSynch
Subsequent update values latched for conversion at internal clock edges
Analog output values stabilize after settling transient
Software control suspends internal clocking at end of channel list
Updating for the next channel list cycle resumes on the next external clock edge.

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Output Triggering Technology

One-Shot Triggering with Channel-List-Clocking Updates

This configuration can update all analog output channels in rapid sequence based on the internal clock. This pattern of updates is repeated each time the external clock goes active, and the entire process can be initiated by triggering.