Output Triggering Technology
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Gated Triggering with Single-Channel Updating
This configuration could be used to generate a pre-programmed output sequence on multiple channels. Each update cycle is initiated by the host system or other external timing source. The internal clock of the Data Acquisition Processor distributes the output values to the channels in rapid sequence.
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Burst mode operation can be used in advanced acoustic imaging applications such as sonar mapping. |
Notes:
- A burst is initiated when the trigger signal is active high at least
tTrigMin - External clocking levels must be held for at least
tExtClkPW - Allow interval
tTCsetupafter triggering to guarantee recognition of clock - After updating the first output channel, the internal clock is used for subsequent updates
- Each channel in the configured channel list receives one update
- Clocking activity suspends at the end of the channel list, and resumes at the arrival of the next external clock edge
- A
COUNTspecification or intentional underflow terminates the updating burst - Analog output values stabilize after a settling transient
- The next updating burst can begin when the trigger level again goes active high