Data Acquisition (DAQ) and Control from Microstar Laboratories

Output Triggering Technology

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System Architecture


DAP Architecture





Output Overview


Single-Sample Clocking


Channel List Clocking





One-Shot Triggering with Single-Sample Updating

This configuration begins generation of a timed output signal when an external triggering signal arrives. When clocking, one update is delivered to the analog output on each clock pulse.

animated example of one-shot triggering with single-sample clocking

Output triggering is a standard feature on all Data Acquisition Processor models that support digital to analog conversion.


  1. Clock source can be external (extClk) or internal onboard (iClk)
  2. Trigger starts low, and must be held active high at least tTrigMin
  3. For external clocks, the clock cycle must be at least tSynch + TIME specification
  4. All clock levels must be held for at least tExtClkPW
  5. Clocking activity begins tTCsetup after triggering goes active
  6. Data from buffer must be fetched and stable at converter before clocking
  7. Update values latched for conversion at clock edges
  8. Analog output values stabilize after settling transient
  9. Unless you configure burst mode, one-shot triggering responds only once