Data Acquisition (DAQ) and Control from Microstar Laboratories

DAP Architecture Features

data acquisition filtering data acquisition software channel architecture enclosures services



System Architecture


DAP Architecture





Architecture Overview


Input Timing & Triggering


Output Timing & Triggering

onboard main cpu section
A/D and Digital section D/A and Digital section
Main Memory section
Input Triggering and Timing section Output Triggering and Timing section
External Bus Interface section
Buffering Buffering
Peripheral Bus Control section Expansion Bus Control section

Point to elements to learn more about them.


Like spaghetti software, "spaghetti hardware" leaves too much to untangle for sophisticated designs. The DAP solution to hardware complexity, like the solution to software complexity, is modularization. Things closely related are packaged together. Things less directly related act through a well-defined interface.

The DAP architecture takes the concepts of modularization and interface far beyond what you will find in ordinary data acquisition products.

Timing and Synchronization

input triggering illustrations

Input timing & triggering

output triggering illustrations

Output timing & triggering

In addition to its onboard precision time reference, the DAP architecture allows external control of triggering, clocking, or both. Triggering determines when action starts and stops. Clocking determines when individual samples are captured or delivered. You can use one, or the other, or both in combination depending on the needs of your application.

There are some subtle differences, but the broad architectural features of triggering and clocking are very similar both for input sampling and for output updating. Triggering can act one time in a "one shot" mode, or suspend and resume repeatedly in a "gated" mode. Timing of individual samples or updates can use the internal clock, an external timing signal, or the unique "channel list clocking" scheme with a mix of both.

Main CPU on wide data bus for efficient data movement and intensive data preprocessing.

Intelligent memory management for buffering large bursts of data.

Host data bus for high-speed transfers of commands and data.

Narrow peripheral bus for digitized data streams and device operation.

Hardware I/O controllers sequence and synchronize low-level device operation.

Hardware I/O controllers sequence and synchronize low-level device operation.

Expansion controller for synchronizing termination and accessory boards.

Input channels collect and buffer data under hardware control.

Output channels deliver data under hardware control.

Icon Simplified processing and device control Icon Consistent real-time response Icon Smart buffering and data management