Channel List Clocking

Technology

System Architecture

DAP Architecture

Processing

Networking

Input Overview

Single-Sample Clocking

Channel List Clocking

Gated

Burst

Triggering with Channel List Clocking

After triggering, clocking is enabled. The first clock pulse initiates capture of the first signal channel. After that, the DAP uses the internal clock for capturing all of other signals in the input channel list sequence.

DAP 5400a can achieve very fast sampling with excellent accuracy.

Engine testing often can use channel list clocking – an optical encoder determines where to measure, and then the DAP collects data on every cylinder at a high rate.

Notes:

Trigger is active high, held for at least tTrigMin
External clock period must be at least TIME x Nchannels + tSynch
All clock levels must be held for at least tExtClkPW
Clocking activity begins tTCsetup after triggering goes active
Begin sampling on the next clock pulse
Switch to internal clock, synchronize after tSynch
Subsequent samples captured on internal clock interval TIME
Digitized values issued after conversion delay
Without burst mode, one-shot triggering responds only once

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Input Triggering Technology

Triggering with Channel List Clocking

After triggering, clocking is enabled. The first clock pulse initiates capture of the first signal channel. After that, the DAP uses the internal clock for capturing all of other signals in the input channel list sequence.