Input Triggering Technology
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Overview of DAP Input Triggering and Clocking
DAP sampling hardware provides three triggering modes and two sampling modes. They can be used in any combination. All triggering and sampling modes are specified in a downloaded DAPL configuration script.
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Evaluating a DAP – like the DAP 5380a – and need more information? You can download the hardware manual from the document download section to get full details. |
- Triggering determines when sampling begins, and, depending on the mode, when sampling ends.
- Burst control determines whether a triggering process is reinitialized after each triggering action.
- Sampling determines the instants at which signals are captured for digitization.
When a digital signal is not available for hardware triggering, and in some situations even when such a signal is available, software triggering provides an alternative with more flexibility.
There are three triggering modes:
- OFF. The default configuration. Sampling begins immediately when a configuration starts.
- ONE-SHOT. A data collection mode for which the first active-high level initiates data collection.
- GATED. A data collection mode for which sampling is enabled when a dedicated digital signal is active high, or disabled when the signal is inactive low.
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Set up your triggering and timing commands using DAPstudio software. |
After sampling starts, samples are captured on each
active-high pulse of the digital sampling clock. The clocking
signal is selected by the CLOCKING configuration.
There are two clocking modes:
- INTERNAL. The default configuration. Sampling is driven by an adjustable digital clocking signal derived from the precision onboard oscillator.
- EXTERNAL. Sampling is driven by a dedicated external digital clocking line.
The two sampling modes are:
- SINGLE CLOCKING (CLC off). One sample is captured per each external digital pulse. Pulses could be irregularly spaced, driven by an encoder device, or controlled by a specially-tuned oscillator.
- CHANNEL LIST CLOCKING (CLC on). The default configuration. After external clocking initiates sampling, the internal clock is used for subsequent samples, until every measurement channel has a sample.