Input Triggering Technology

Input Triggering in Gated Mode

While the triggering signal is active high, clocking activity is enabled. When the triggering signal drops to inactive low, clocking activity is suspended.

Notes:

1. Onboard clocking is shown, but clocking could be external
2. Trigger is active high, held for at least tTrigMin to guarantee capture of a sample
3. All clock levels must be held for at least tExtClkPW
4. When using external clocking, the period must be no shorter than tSynch + TIME specification to allow onboard timing to synchronize
5. Sampling activity can respond to clocking signal tTCsetup after triggering goes active
6. After sampling becomes active, sampling occurs on clock pulses
7. Digitized values issued after conversion delay
8. In each cycle, there is an period of length tTrigMax during which a low trigger level deactivates clocking
9. While the gated trigger remains low, sampling activity does not respond to the clock signal

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